This invention relates to emitter coupled logic (ECL) circuits.
In standard ECL circuits, two switching transistors are connected at their emitters with the base of one transistor being connected to a reference voltage between the digital high and low voltage states. The base of the other transistor is connected to an input voltage. The connected emitters are connected to a current source transistor which provides the current to the two switching transistors (the gate current). The base of this current source transistor is connected to a current source voltage, V.sub.cs. The collectors of the emitter coupled transistors are each connected via a resistance to a positive power supply. An output is obtained at the collector of each emitter coupled transistor upon application of an input voltage. One collector provides a non-inverting output, and the other collector provides an inverting output. Each output is often connected to an emitter follower transistor which provides greater current capacity for the output. The output is then taken from the emitter of each emitter follower, which is also connected to a current source transistor.
Each current source transistor coupled to an emitter follower has its base connected to the same current source voltage, V.sub.cs. This provides for an equal load current to flow through each of such current source transistors. Upon an input transition from a high to a low state, or from a low to a high state, the outputs also change state accordingly. The speed with which the outputs change states depends upon the capacitance of the load connected to the output. If the output goes from a low to a high state, it must charge up the load capacitance. Conversely, if an output goes from a high to a low state, it must discharge the load capacitance. The load capacitance is charged by current from the emitter follower transistor and the supply voltage source. The load capacitance is discharged by current passing through the current source transistor to ground.
The speed with which the output changes state depends on the time which it takes the transistor to charge or discharge the load capacitance. This time is dependent upon the current flow as can be seen from the equation: EQU i=c*dv/dt (1)
where:
i=current; PA1 c=capacitance; PA1 dv=change in voltage; and PA1 dt=change in time.
Rearranging equation (1) yields the following equation: EQU dt=c*dv/i (2)
Thus, it can be seen that the greater the current i, the smaller the change in time for a given change in voltage.
Upon an output going to a low state, the amount of current that can be used to discharge the capacitance is determined by a current source transistor. This current flow is fixed by the current source voltage and the value of the resistance coupled to the current source transistor. The speed of a transition to a low state is limited by this fixed current flow.
When an output goes to a high state the output capacitance must be charged. Some of the current from the supply voltage used to charge such capacitance is lost by going through the current source transistor. The loss of this current results in a slow transition time to a high state. As can be seen by the above discussion, ECL gates have inherently poor speed-power products.